[AKD4712-A] 2012/06 -1- general description akd4712 is an evaluation board for quickly evaluating the ak4712, a high definition a/v cap-less line driver. evaluation requires audio/video analog anal yzer/generator and a power supply. ? ordering guide AKD4712-A --- ak4712 evaluation board (control software and usb cable are included in this package.) function ? rca connectors for analog audio output ? xlr connectors for analog audio input ? rca connectors for sd/hd video input/output ? usb connector for serial control interface 3.3v pic18f4550 a inl+ ak4712 +5v vd1 +5v 3.3v regulator usb port a inl- a inr+ a inr- encrca encpb encpr ency 5.0v hdy hdpr hdpb rcavout tvoutr tvoutl regulator regulator +5v 3.3v vd2 vvd vss vss2 figure 1. akd4712 block diagram circuit diagram and pcb layout are a ttached at the end of this manual. a kd4712- a a k4712 evaluation board rev.0
[AKD4712-A] 2012/06 -2- evaluation board manual ? operation sequence 1) set up the power supply lines. name of jack color of jack voltage used for comments default of jack +5v yellow +5v power supply of ak4712 should always be connected +5v vd1 red +3.13 +3.47 vd1 of ak4712 should be connected when jp9 (vd1) is open. should be open when jp9 (vd1) is short. short vd2 red +3.13 +3.47v vd2 of ak4712 should be connected when jp11 (vd2) is open. should be open when r51 (vd2) is short. short vvd red +3.13 +3.47v vvd of ak4712 hdvvd of ak4712 should be connected when jp12 (vvd) is open. should be open when jp12(vvd) is short. short d3.3v red +3.13 3.47v logic power supply should be connected when jp10 (d3.3v) is open. should be open when jp10 (d3.3v) is short. short vss black 0v analog ground should always be connected 0v vss2 black 0v analog ground should always be connected when vd2 is connected. open dgnd black 0v digital ground should be connected when jp8 (gnd) is open. should be open when jp8(gnd) is short. open table 1.power supply lines each supply line should be distributed from the power supply unit. 2) set-up jumper pins. (see the following.) 3) power on. ak4712 should be reset once by bringing sw1 ?l? upon power-up. ? jumper pin settings [jp1] (ainl+_sel): ainl+ pin input select input1: r=20k input2: r=0 [jp2] (ainr+_sel): ainr+ pin input select input1: r=20k input2: r=0 [jp3] (muten/scl_sel): sda/muten pin input select sda: sda muten: muten *when i2csel=?l?(hard wired), sda/muten pin is used for audio mute. [jp4] (uvp/scl_sel): scl/uvp (under voltage protection) scl: scl uvp: uvp *when i2csel=?l?, uvp pin can be used for under voltage protection.
[AKD4712-A] 2012/06 -3- [jp5] (gnd): ainl- pin input select open: j5 (ainl): 3pin short: gnd (not to use) [jp6] (gnd): ainr- pin input select open: j13 (ainr): 3pin short: gnd (not to use) [jp7] not for use [jp8] (gnd): analog ground and digital ground open: separated short: common. (the connector ?dgnd? can be open.) [jp9] (vd1): regulator (+3.3v) or vd1 connector open: vd1 pin is supplied from vd1 connector. short: vd1 pin is supplied from regulator (+3.3v). (the connector ?vd1? can be open.) [jp10] (d3.3v): regulator (+3.3v) or d3.3v connector open: logic voltage is supplied from d3.3v connector. short: logic voltage is supplied form regulator (+3. 3v). (the connector ?vcc? can be open.) [jp11] (vd2): regulator (+3.3v) or vd2 connector open: vd2 pin is supplied from vd2 connector. short: vd2 pin is supplied from regulator (+3.3v). (the connector ?vd1? can be open.) [jp12] (vvd): regulator (+3.3v) or vvd connector open: vvd and hvvd pins are supplied from vvd connector. short: vvd and hvvd pins are supplied from regulator (+3.3v) (the connector ?vvd? can be open.) [jp13] (reg-sel): regulator (+3.3v) from t2 or t3 t2: regulator supplied from t2. t3: regulator supplied from t3. the t2 regulator can supply 3.3v to all circuits by shorting jp9, jp10, jp11 and jp12 and supplying 5v to +5v connector. ? dip sw function no. pin off on default 1 muten audio mute muten bit l: mute h: unmute (default) on 2 i2csel i2c control enable pin l: disable (hard wired) (default) h: enable (i2c) off when the i2csel pin = ?l? (hard wire d), the sda/muten pin is used for audio mute. muten bit is ignored. muten pin audio output status l mute h unmute (1) hard wired mode when the i2csel pin= ?h? (i2c), muten b it is used for audio mute. the sda/muten pin is used for control data input.
[AKD4712-A] 2012/06 -4- muten bit audio output status 0 mute 1 unmute (default) (2) i2c mode ? toggle sw function [sw2] (pdn): resets ak4712. keep ?h? during normal operation. ? board control the ak4712 can be controlled via usb port with a pc. connect port1 with pc by usb cable included in AKD4712-A package. the control software is also included. ? analog input/output list signal name note audio input j5(ainl+, ainl-), j12(ainr+, ainr-) typ. 2vrms output j4 (tvoutl), j8 (tvoutr) typ. 2vrms video input j2 (ency), j9 (encpr), j6 (encpb), j13 (encrca) max. 1.25vpp output j3 (hdy), j7 (hdpb), j11(hdpr), j14(rcavout) max. 2.5vpp table 2. analog input/output list
[AKD4712-A] 2012/06 -5- control software manual evaluation board and control software settings 1. set up the evaluation board as needed, according to the previous terms. 2. connect the evaluation board to a pc with usb cable. usb control is recognized as hid (human interface device) on pc. when it is not recognized properly, please reconnect the evaluation board to pc. 3. insert the cd-rom labeled ?AKD4712-A evaluation kit? into the cd-rom drive. 4. access the cd-rom drive and double-click the icon ?AKD4712-A.exe? to open the control program. 5. begin evaluation by following the procedure below. [supported os] windows 2000 / xp 64bit os is not supported. windows 95 / 98 / me / nt are not supported.
[AKD4712-A] 2012/06 -6- operation screen 1. start up the control program following the above procedure. 2. after power is supplied to the evaluation board, ak4712 must be reset once by bringing sw2 (ak4712-pdn) from ? l ? to ? h ? . 3. the control program operation screen is shown below figure 2. control program window operation overview register map and testing are controlled by this control soft ware. these controls may be selected by the upper tabs. frequently used buttons, such as the register initializing button ?write default?, are located outside of the switching tab window. refer to the ? dialog box ? section for details of each dialog box setting. button functions 1. [port reset]: reset connection to pc click this button after the control software starts up and the evaluation board is connected to the pc via usb cable. 2. [write default]: register initialization
[AKD4712-A] 2012/06 -7- use this button to initialize the registers when the device is reset by a hardware reset. 3. [all write]: execute write command for all registers displayed. 4. [all read]: execute read comma nd for all registers displayed. 5. [save]: save current re gister settings to a file. 6. [load]: execute data write from a saved file. 7. [all reg write]: [all reg write] dialog box pops up. 8. [data r/w]: [data r/w] dialog box pops up. 9. [read]: read current register settings and display to the register area (on the right of the main window). this is different from [all read] button as it does not reflect to the register map. it only displays the current register values in hexadecimal numbers.
[AKD4712-A] 2012/06 -8- tab functions 1. [reg]: register map this tab is for register read and write. each bit on the register map is a push-button switch. button down indicates ?h? or ?1? and the bit name is show n in red (when read-only the name is shown in dark red). button up indicates ?l? or ?0? and the bit name is shown in blue (when read-only the name is shown in gray) grayed out registers are read-only re gisters. they can not be controlled. the registers which are not defined on the datasheet are indicated as ?---?. figure 3. [reg] window
[AKD4712-A] 2012/06 -9- 1-1. [write]: data write dialog select the [write] button located on th e right of the each corresponding address when changing two or more bits on the same address simultaneously. click the [write] button for the register pop-up dialog box shown below. when the checkbox next to the register is checked, the data will become ?h ? or ?1?. when the checkbox is not checked, the data will become ?l? or ?0?. click [ok] to write the set values to the registers, or click [cancel] to cancel this setting. figure 4. [register set] window 1-2. [read]: data read click the [read] button located on th e right of the each corresponding addr ess to execute a register read. the current register value will be displayed in the re gister window as well as in the upper right hand debug window. button down indicates ?h? or ?1? and the bit name is shown in red (when read only the bit name is shown in dark red). button up indicates ?l? or ?0? and the bit name is shown in blue (when read only the bit name is shown in gray) please be aware that button statuses will be changed by a read command.
[AKD4712-A] 2012/06 -10- 2. [tool]: testing tools evaluation testing tools are available in this tab. click the corresponding butt on for each testing tool. figure 5. [tool] window
[AKD4712-A] 2012/06 -11- 2-1. [repeat test]: repeat test dialog click the [repeat test] button in the tool tab to open the repeat test dialog shown below. a write repeat test can be executed by this dialog. figure 6. [repeat test] window [start] button : start repeat test. a dialog for saving a file of the test result will open when this button is clicked. name the file. test will start after inserting a filename. [close] button : close dialog and finish process. [address] box : input write data address in hexadecimal numbers. [start data] box : input start data in hexadecimal numbers. [end data] box : input end data in hexadecimal numbers. [step] box : input data write step interval. [repeat count] box : input number of repeat cycles for the test writing. [up and down] box : data write flow is changed as below. ? checked: writes in step interval from the start data to the end data and turns back at the end data to the start data. [example] start data = 00, end data = 05, step = 1, [ ]?for 1 count. data flow: [00 01 02 03 04 05 05 04 03 02 01 00] x repeat count number ? not checked: writes in step interval from the start data to the end data and finishes writing. [example] start data = 00, end data = 05, step = 1, [ ]?for 1 count. data flow: [00 01 02 03 04 05] x repeat count number [sampling frequency] box: select sampling frequency from 44.1khz/48khz [count] box : indicates the count number during a repeat test. [lch level] box : indicates the lch level during a repeat test.
[AKD4712-A] 2012/06 -12- 2-2. [loop setting]: loop dialog click the [loop setting] button in the tool tab to open the l oop setting dialog shown below. a write test can be executed. figure 7. [loop] window [ ok ] button : start loop test. [ cancel ] button : close dialog and finish process. [ address ] box : input data write address in hexadecimal numbers. [ start data ] box : input start data in hexadecimal numbers. [ end data ] box : input end data in hexadecimal numbers. [ interval ] box : input data write interval time. [ step ] box : input data write step interval. [ mode select ] box : mode select check box. ? checked: write in step interval from the start data to the end data and turn back at the end data to start data. [example] start data = 00, end data = 05, step = 1 data flow: 00 01 02 03 04 05 05 04 03 02 01 00 ? not checked: write in step interval from the start data to the end data and finish write. [example] start data = 00, end data = 05, step = 1 data flow: 00 01 02 03 04 05
[AKD4712-A] 2012/06 -13- dialog box 1. [all req write]: all reg write dialog box click [all reg write] button in the main window to open register setting file window shown below. register setting files saved by [save] button may be applied. figure 8. [all reg write] window [open (left)]: select a register setting file (*.akr). [write]: execute register write with selected setting file. [write all]: execute register write with all selected setting files. selected files are executed in descending order. [help]: open help window. [save]: save register setting file assignment. file name is ?*.mar?. [open (right)]: open saved register setting file assignment ?*. mar?. [close]: close dialog box and finish process. ~ operating suggestions ~ 1. files saved by [save] button and opened by [open] button on the right of the dialog ?*.mar? should be stored in the same folder. 2. when register settings are changed by [save] button in the main window, re-read the file to reflect new register settings.
[AKD4712-A] 2012/06 -14- 2. [data r/w]: data r/w dialog box click the [data r/w] button in the main window for data read/write dialog box. data is written to the specified address. figure 9. [data r/w] window [address] box: input data write address in hexadecimal numbers. [data] box : input write data in hexadecimal numbers. [mask] box : input mask data in hexadecimal numbers. this value ?anded? with the write data becomes the input data. [write]: write data generated from data and mask va lue is written to the address specified in ?address? box. [read]: read data from the address specified in ?address? box. the result will be shown in the read data box in hexadecimal numbers. [close]: close dialog box and finish process. data write will not be executed unless [write] is clicked. *the register map will be updated after executing the [write] or [read] command.
[AKD4712-A] 2012/06 -15- measurement results ? audio [measurement condition] ? measurement unit : audio precision sys-2722 ? bw : 20hz 20khz ? power supply : +5v=5v, vd1=3.3v, vd2=3.3v, vvd=3.3v ? interface : input: cannon, output: bnc ? temperature : room ? volume gain : 0db ? measurement signal line path: ainl/ainr tvoutl/tvoutr parameter input signal measurement filter results lch [db] results rch [db] s/(n+d) (at 2vrms output) 1khz, 0dbfs 20klpf 104.2 104.6 dr 1khz, -60dbfs 22klpf, a-weighted 109.2 109.1 s/n no input 22klpf, a-weighted 109.2 109.1 plots figure 1-1. fft (1khz, 0dbfs input) at 2vrms output figure 1-2. fft (1khz, -60dbfs input) figure 1-3. fft (noise floor) figure 1-4. thd+n vs. input level (fin=1khz) figure 1-5. thd+n vs. fin (input level=0dbfs) figure 1-6. linearity (fin=1khz) figure 1-7. frequency response (input level=0dbfs) figure 1-8. crosstalk (input level=0dbfs)
[AKD4712-A] 2012/06 -16- ? video [measurement condition] ? signal generator : sony tectronix tg2000 ? measurement unit : sony tectronix vm700t ? power supply : +5v=5v, vd1=3.3v, vd2=3.3v, vvd=3.3v ? interface : inpu t: bnc, output: bnc ? temperature : room ? measurement signal line path: s/n: encrca rcavout dg, dp: encrca rcavout plots figure 2-1. noise spectrum sd/hd (input=0% flat field, bw=15khz to 5mhz, filter=uni-weighted) figure 2-2. dg, dp (input= modulated 5 step) parameter input signal measurement filter results unit s/n 0% flat field bw=15khz to 5mhz filter=uni-weighted 75.2 db dg modulated 5 step min: 0.00 max: 1.34 % dp modulated 5 step min: -0.04 max: 0.16 deg.
[AKD4712-A] 2012/06 -17- plots (audio) ak4712 ainl/ainr ? tvoutl/tvoutr: fft: fin=1khz, input level=0db -180 +0 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 1 - 1. fft (fin=1khz, input level=0db) ak4712 ainl/ainr ? tvoutl/tvoutr: fft: fin=1khz, input level=-60db -180 +0 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 1 - 2. fft (fin=1khz input level=-60db)
[AKD4712-A] 2012/06 -18- ak4712 ainl/ainr ? tvoutl/tvoutr: fft: no-input -180 +0 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 1 - 3. fft (noise floor) ak4712 ainl/ainr ? tvoutl/tvoutr: thd+n amplitude vs input amplitude: fin=1khz -120 -80 -116 -112 -108 -104 -100 -96 -92 -88 -84 d b r a -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbr figure 1 - 4. thd+n vs. input level (fin=1khz)
[AKD4712-A] 2012/06 -19- ak4712 ainl/ainr ? tvoutl/tvoutr: thd+n amplitude vs input frequency: input level=0db -120 -80 -116 -112 -108 -104 -100 -96 -92 -88 -84 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 1 - 5. thd+n vs. input frequency (input level=0db) ak4712 ainl/ainr ? tvoutl/tvoutr: linearity: fin=1khz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbr figure 1 - 6. linearity (fin=1khz)
[AKD4712-A] 2012/06 -20- ak4712 ainl/ainr ? tvoutl/tvoutr: frequency response: input level=0dbr -0.5 +0.5 -0.45 -0.4 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 +0 +0.05 +0.1 +0.15 +0.2 +0.25 +0.3 +0.35 +0.4 +0.45 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 1 - 7. frequency response (input level=0db) ak4712 ainl/ainr ? tvoutl/tvoutr: crosstalk: fin=1khz, input level=0dbr / no-input -140 -70 -135 -130 -125 -120 -115 -110 -105 -100 -95 -90 -85 -80 -75 d b 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 1 - 8. crosstalk (input level=0db)
[AKD4712-A] 2012/06 -21- plots(video) ak4712 encv ? tvout: s/n: input signal=0% flat field, bw=15khz to 5mhz, filter=uni-weighted figure 2 - 1a. rcavout noise spectru m (input=0% flat field, bw=15khz to 5mhz, filter=uni-weighted) figure 2 - 1b. hdy noise spectrum (input=0% flat fi eld, bw=15khz to 5mhz, filter=uni-weighted)
[AKD4712-A] 2012/06 -22- figure 2 - 1c. hdpr noise spectrum (input=0% flat field, bw=15khz to 5mhz , filter=uni-weighted) figure 2 - 1d. hdpb noise spectrum (input=0% flat field, bw=15khz to 5mhz , filter=uni-weighted)
[AKD4712-A] 2012/06 -23- ak4712 encrca ? rcavout: dg, dp: input signal=modulated 5 step figure 2 - 2. dg, dp (input signal= modulated 5 step)
[AKD4712-A] 2012/06 -24- revision history important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application exampl es of the semiconductor products. you are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your e quipments. akm assumes no responsibility fo r any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the applica tion or use of such information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility fo r such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to functi on or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products , who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above conten t and conditions, and the buyer or distributor agrees to assume any and all responsib ility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification. date (yy/mm/dd) manual revision board revision reason contents 12/06/19 km111300 0 first edition
5 5 4 4 3 3 2 2 1 1 d d c c b b a a vss connect the back tab with vss ainl+_sel input1 input2 input1 input2 ainr+_sel uvp/scl_sel scl uvp muten/scl_sel muten sda vss vss vss vss2 vss hdpr hdpb rcavout v d 2 v d 1 ainr+ ainr- i2csel tvoutr hdy e n c r c a e n c p b e n c p r e n c y s d a m u t e n s c l p d n ainl- ainl+ tvoutl vvd title size document number rev date: sheet of ak4712 0 AKD4712-A a3 1 4 thursday, june 14, 2012 title size document number rev date: sheet of ak4712 0 AKD4712-A a3 1 4 thursday, june 14, 2012 title size document number rev date: sheet of ak4712 0 AKD4712-A a3 1 4 thursday, june 14, 2012 + c10 4.7u r11 10k r5 20k r12 10k r7 75 r1 10k + c2 4.7u c8 1.0u c9 1.0u c4 0.1u r3 0 r10 75 r8 75 c6 1.0u r2 20k c12 0.1u c5 1.0u r15 10k jp3 cn1 (open) 1 2 3 4 5 6 7 8 9 r4 10k jp1 c7 1.0u u1 ak4712 vvee 1 vreg 2 hdy 3 hdpr 4 hdpb 5 rcavout 6 vvd 7 e n c r c a 8 e n c p b 9 e n c p r 1 0 e n c y 1 1 s d a / m u t e n 1 2 s c l / u v p 1 3 p d n 1 4 ainl+ 21 ainl- 20 tvoutl 19 i2csel 18 tvoutr 17 ainr- 16 ainr+ 15 v c n 2 8 v c p 2 7 v d 2 2 6 v d 1 2 5 c p 2 4 c n 2 3 v e e 2 2 r6 75 tp1 uvp r16 1.6k cn2 (open) 1 2 3 4 5 6 7 8 9 r13 20k cn4 (open) 1 2 3 4 5 6 7 8 9 c3 0.1u jp4 r48 22k r14 0 + c1 4.7u cn3 (open) 1 2 3 4 5 6 7 8 9 c11 0.1u jp2 r9 20k
5 5 4 4 3 3 2 2 1 1 d d c c b b a a video intput video output audio output audio intput vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss agnd vss agnd hdy hdpr hdpb rcavout ainr- tvoutl tvoutr ainl+ encrca ainl- ainr+ ency encpb encpr title size document number rev date: sheet of audio video input / output 0 AKD4712-A a3 2 4 thursday, june 14, 2012 title size document number rev date: sheet of audio video input / output 0 AKD4712-A a3 2 4 thursday, june 14, 2012 title size document number rev date: sheet of audio video input / output 0 AKD4712-A a3 2 4 thursday, june 14, 2012 j12 ainr 2 2 3 3 1 1 + c22 0.47u + c14 (short) r24 75 r18 75 j2 ency 1 2 3 4 5 + c16 0.47u + c18 (short) c21 0.1u c15 0.1u j11 ainr+ 1 2 3 4 5 j3 hdy 1 2 3 4 5 j6 encpb 1 2 3 4 5 j8 tvoutr 1 2 3 4 5 r22 10k j4 tvoutl 1 2 3 4 5 j7 hdpb 1 2 3 4 5 jp5 gnd r21 330 r23 75 + c20 0.47u j13 encrca 1 2 3 4 5 jp6 gnd j9 encpr 1 2 3 4 5 r19 10k r20 75 j10 hdpr 1 2 3 4 5 + c13 0.47u j14 rcavout 1 2 3 4 5 j1 ainl+ 1 2 3 4 5 c17 0.1u r17 330 j5 ainl 2 2 3 3 1 1 c19 0.1u
5 5 4 4 3 3 2 2 1 1 d d c c b b a a silk-screen 1:vdd 2:mclr 3:pgd 4:pgc 5:gnd scl sda(ack) sda xti xto usb-rst scl sda sda(ack) pdn h l h l muten i2csel dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd d3.3v d3.3v d3.3v scl sda d3.3v d3.3v pdn d3.3v i2csel muten title size document number rev date: sheet of up-i/f 0 AKD4712-A a3 3 4 thursday, june 14, 2012 title size document number rev date: sheet of up-i/f 0 AKD4712-A a3 3 4 thursday, june 14, 2012 title size document number rev date: sheet of up-i/f 0 AKD4712-A a3 3 4 thursday, june 14, 2012 port2 10pin-ctrl a1-10pa-2.54dsa(open) 1 3 5 7 9 10 8 6 4 2 r34 470 r39 100k r50 0 c33 470n r33 10k + c24 10u r41 51 r38 470 u4 74hc14 gnd 7 1a 1 3a 5 5a 11 5y 10 3y 6 1y 2 2y 4 4y 8 6y 12 6a 13 4a 9 2a 3 vcc 14 u3 74hc07 1a 1 2a 3 3a 5 4a 9 5a 11 6a 13 vcc 14 gnd 7 1y 2 2y 4 3y 6 4y 8 5y 10 6y 12 r37 0 r32 10k port1 usb(b type) vusb 1 d- 2 d+ 3 gnd 4 r 2 6 5 1 ( o p e n ) r49 10k c35 0.1u r 2 7 5 1 ( o p e n ) r42 51 c49 0.1u tp2 sda r35 51 r 2 8 5 1 ( o p e n ) tp3 scl d1 hsu119 k a x1 20mhz r36 51 jp7 1 2 3 4 5 r 3 0 1 0 k c27 0.1u sw 2 2 1 3 c28 1u sw 1 1 2 4 3 r45 10k t 1 5 v = > 3 . 3 v t k 7 3 6 3 3 a m e n c 1 v o u t 2 p c l 3 g n d 4 n c 8 v i n 7 n c 5 v c o n t 6 pic18f4550 tqfp 44-pin u2 pic18f4550 rc7/rx/dt/sdo 1 rd4/spp4 2 rd5/spp5/p1b 3 rd6/spp6/p1c 4 rd7/spp7/p1d 5 v s s 0 6 v d d 0 7 rb0/an12/int0/flt0/sdi/sda 8 rb1/an10/int1/sck/scl 9 rb2/an8/int2/vmo 10 rb3/an9/cpp2/vpo 11 nc/icck/icpgc 12 nc/icdt/icpgd 13 rb4/an11/kbi0/csspp 14 rb5/kbi1/pgm 15 rb6/kbi2/pgc 16 rb7/kbi3/pgd 17 mclr_n/vpp/re3 18 ra0/an0 19 ra1/an1 20 ra2/an2/vref-/cvref 21 ra3/an3/vref+ 22 ra4/t0cki/c1out/rcv 23 ra5/an4/ss_n/hlvdin/c2out 24 re0/an5/ck1spp 25 re1/an6/ck2spp 26 re2/an7/oespp 27 v d d 1 2 8 v s s 1 2 9 osc1/clki 30 osc2/clko/ra6 31 rc0/t1oso/t13cki 32 nc/icrst_n/icvpp 33 nc/icports 34 rc1/t1osi/ccp2/uoe_n 35 rc2/ccp1/p1a 36 vusb 37 rd0/spp0 38 rd1/spp1 39 rd2/spp2 40 rd3/spp3 41 rc4/d-/vm 42 rc5/d+/vp 43 rc6/tx/ck 44 c32 22p c30 0.1u r 2 9 1 0 k r47 10k + c25 10u c34 0.1u r43 0 r46 10k c29 0.1u c31 22p r 3 1 1 0 k r40 51 c23 2.2u r25 4.7k r44 0 c26 0.1u
5 5 4 4 3 3 2 2 1 1 d d c c b b a a vss2 +5v vd1 vd2 vvd d3.3v vss vss2 dgnd reg1 reg2 reg_sel +5v vd2 vvd d3.3v vd1 vd1 d3.3v dgnd dgnd dgnd vss vss vss vss vss +5v vvd vss vd2 vss2 vss2 vss vss vd1 d3.3v vvd vd2 title size document number rev date: sheet of power supplly 0 AKD4712-A a3 4 4 thursday, june 14, 2012 title size document number rev date: sheet of power supplly 0 AKD4712-A a3 4 4 thursday, june 14, 2012 title size document number rev date: sheet of power supplly 0 AKD4712-A a3 4 4 thursday, june 14, 2012 t2 lm1117idtx-3.3 out 3 g n d 2 in 1 tp6 vd2 + c36 47u tp16 vss tp7 vd2 + c37 47u 1 2 + c42 47u 1 2 j17 tj563-r 1 + c41 10u c45 0.1u tp8 vvd jp10 d3.3v j15 tj563-y 1 tp9 vvd j18 tj563-r 1 j16 tj563-r 1 tp14 vss l2 (short) 1 2 + c48 47u 1 2 tp15 vss jp9 vd1 j20 tj563-bk 1 jp12 vvd c46 0.1u tp10 d3.3v tp11 vss jp11 vd2 l4 (short) 1 2 j22 tj563-bk 1 c39 0.1u t3 lm1117idtx-3.3 out 3 g n d 2 in 1 tp17 vss2 l1 (short) 1 2 jp13 j21 tj563-bk 1 tp4 vd1 tp12 vss + c43 47u 1 2 + c47 10u tp18 dgnd c40 0.1u tp13 vss tp5 vd1 jp8 gnd l3 (short) 1 2 + c44 10u + c38 10u j19 tj563-r 1
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